Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device involves formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper (Cu), since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, e.g., Al-based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in integrated circuit (IC) product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than silicon dioxide.
The damascene processes used in forming interconnect and via structures face challenges as the size of devices and associated interconnects shrinks. In typical formation of an interconnect or via, a seed layer is formed on surfaces of a trench prior to forming the conductive material, e.g., copper, etc., in the trench. However, sufficient seed layer coverage on the patterned dielectric is difficult to achieve with ultra thin seed layers, e.g., seed layers having a thickness less than 2 nm. Moreover, void-free plating is becoming difficult due to poor liner and/or seed coverage, and also due to high aspect ratio (AR) challenges for plating. For example, interconnects and/or vias formed in high AR trenches may detrimentally experience pinch-offs, voids, etc., if the liner is too thick at the top of the trench or via hole.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.